A liquid crystal display (LCD) includes an LCD panel formed with liquid crystal cells and pixel elements with each associating with a corresponding liquid crystal cell. These pixel elements are substantially arranged in the form of a matrix having gate lines in rows and data lines in columns. The LCD panel is driven by a driving circuit including a gate driver and a data driver. The gate driver generates a plurality of gate signals (scanning signals) sequentially applied to the gate lines for sequentially turning on the pixel elements row-by-row. The data driver generates a plurality of source signals (data signals), i.e., sequentially sampling image signals, simultaneously applied to the data lines in conjunction with the gate signals applied to the gate lines for aligning states of the liquid crystal cells on the LCD panel to control light transmittance therethrough, thereby displaying an image on the LCD.
In such a driving circuit, a bi-directional shift register is usually utilized in the gate driver to generate the plurality of gate signals for sequentially driving the gate lines, so as to allow a positive or a reverse display image. Typically, a plurality of 2-to-2 bi-directional control circuits is employed in the bi-directional shift register to control the scanning direction, forward or backward, of the plurality of gate signals.
FIG. 1 illustrates a conventional bi-directional shift register, where the 2-to-2 bi-directional control circuit has two input terminals P and N, and two output terminals D1 and D2, and are operably controlled by two control nodes Bi and XBi. The control nodes Bi and XBi are two DC signals set to have opposite polarities, such as a high level voltage and a low level voltage.
FIG. 2 shows a conventional two-way shift register with a set of shift register circuits S1 to SN. The control signal lines Bi1 and Bi2 receive two complementary control voltage signals directed to each control node Bi and XBi. When the control node Bi receives, from the control signal line Bi1, a control voltage signal of a high level voltage level, the control node XBi would complementary receive, from the control signal line Bi2, a control voltage signal of a low level voltage level. Likewise, when the control node XBi receives, from the control signal line Bi2, a control voltage signal of a high level voltage level, the control node Bi would complementary receive, from the control signal line Bi1, a control voltage signal of a low level voltage level.
However, over a period of time, transistors in shift register circuits S1 to SN connected to Bi or XBi would deteriorate due to electrical degradation caused by the high level voltage. Such deterioration or degradation of electrical characteristics, particularly for amorphous silicon (a-Si) components, is likely to lead to a circuit breakdown or operation failure.
Therefore, a heretofore unaddressed need exists in the art to address the aforementioned deficiencies and inadequacies.